The present inventive concept relates to integrated circuit devices, and, in particular, to integrated circuit memory devices.
Memory devices that employ variable resistance materials include resistive random access memories (RRAM), phase changeable random access memories (PRAM), ferroelectric random access memories (FRAM), magnetic random access memories (MRAM), etc. While dynamic random access memories (DRAM) and/or flash memory devices may store data based on stored charges, the nonvolatile memory devices listed above may store data based on a variation in the resistance of a variable resistance material (RRAM), a phase changeable material having amorphous and crystalline states (PRAM), a ferroelectric material having different polarization states (FRAM), and/or a magnetic tunnel junction (MTJ) film of a ferroelectric material having different magnetized states (MRAM).
A memory cell array may include a plurality of such memory elements, also referred to herein as memory cells. Each memory cell is coupled between a word line and a bit line. However, as memory devices are scaled-down, the resistances of the bit lines and/or word lines may increase, for example, due to the relative decrease in the dimensions of the bit lines and/or word lines. Moreover the line resistances of the memory cells may differ based on the location of the memory cells. For example, memory cells that are further from the row and/or column decoders may have greater line resistances than memory cells that are closer to the row and/or column decoders, due to the differences in the lengths of the bit lines and/or word lines coupled thereto.